These Schottky clamped TTL-MSI circuits are designed for use in high-performance memory decoding or data routing applications that require very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the impact of system decoding. When using high-speed memories with fast enable circuits, the delay times of these decoders and the enable times of the memories are usually less than the typical access times of the memories. This means that the effective system delay introduced by the Schottky clamped system decoder is negligible.
This circuit consists of two separate two-wire to four-wire decoders. The active low enable input can be used as a data line in demultiplexing applications.
All of these decoders/demuxes have fully buffered inputs, with each input representing only a normalized load on its driver circuit. All inputs feature high-performance Schottky diode clamps to suppress line ringing and simplify system design.
