Overview

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    These monolithic, synchronous reversible (up/down) counters have a complexity of 55 equivalent gates. The 74LS193 is a 4-bit binary counter. Synchronous operation is provided by clocking all flip-flops simultaneously so that the outputs change in unison with each other when the steering logic so directs. This mode of operation eliminates the output count spikes normally associated with asynchronous (ripple-dockl) counters. Each of the four material outputs is triggered by a low-to-high level transition of the « count (dockl) input by a L flip-flop. The direction of the count is determined by which count input pulse is white and the other count input pulse is high. That is, each output can be preset to lovel by inputting the desired data at the data input when the load input M is low. The output will change to coincide with the data input of tno count pulse. This feature allows the counter to be used as a modulo-N divide-by-N divider simply by modifying the count length using the preset input. A clear input is provided which, when applied high, forces all outputs to a low level. The clear function is independent of the count and load inputs. The dear, count, and load inputs are buffered to reduce driver requirements. This reduces the number of dock drivers, etc. required for long words. These counters are designed to be cascaded without the need for external data. Both the borrow and carry outputs can be cascaded for both up and down count functions. When the counter underflows, the borrow output produces a PCJTSEP with a width equal to that of the countdown input. Similarly, when an overflow condition exists, the cany output produces a pulse with a width equal to that of the up count input. Counters can then be easily cascaded by feeding the borrow and carry outputs to the countdown and countdown inputs of subsequent counters, respectively.