Overview

Product details

    Thww-dvvicw contains two indepMXJent j-k neQattve~fldue* flip-flops. Preset and clear the luw level of the input SOT or reset the output regsrdlesB of the tevsis of the other inputs. When preset and delay are indrive (high), the data at the J and K inputs that meet the setup time R are transferred to the output on the negative edge of the clock pulse. The clock trigger occurs on vdtago tsvef and has no direct relationship with the rise time of the dock pulse. After the hold time intevval, the data at the J and K inputs may be affected by the vel3 at the I» output.