Overview

Product details

    XD74LS165 is an 8-bit serial shift register that shifts data along the Q-A direction to the Q-H direction during timing. Each stage is accessed in parallel via eight separate direct data inputs enabled by a low level on the Shift/Load (SH/LD) input. These registers also have a gated clock (CLK) input and a complementary output on bit eight. All inputs are diode clamped to minimize transmission line effects, simplifying system design.
Clocking is implemented via a two-input positive NOR gate, allowing one input to be used as a clock suppression function. Holding either clock input high inhibits the clock, holding either clock input low and holding SH/LD high enables the other clock input. Clock Inhibit (CLK INH) should only change high when CLK is high. As long as SH/LD is high, parallel loading is disabled. When SH/LD is low, the data at the parallel input terminal is loaded directly into the register, regardless of the levels of CLK and CLK INH. or serial (SER) input.