Overview

Product details

Inputs are buffered to reduce drive requirements to a 74 or 74LS Series standard load respectively. Input clamping diodes minimize switching transients and simplify system design. The complexity of this parallel input or serial input, serial output shift register is equivalent to 77 equivalent gates on a single chip. This device has a gated clock input and an override clear input. Establish parallel input or series input mode via shift/load input. When high, this input enables the serial data input and shifts the 8 flip-flops serially with each clock pulse. When low, parallel (wideside) data input is enabled, synchronous loading occurs on the next clock pulse, and serial data flow is inhibited during parallel loading. Of course this allows the system clock to free run and the registers can be stopped along with other clock inputs when commanded. The clock inhibit input should be changed to high only when the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.