Overview

Product details

    The XD4059 Standard "A" Series type is a divide-by-N down counter that can be programmed to divide the input frequency by any number "N" between 3 and 15,999. The output signal is a pulse, one clock cycle wide, with a frequency equal to the input frequency divided by N. This single output has TTL drive capability. The down counter is preset via 16 disturb inputs. The three mode select inputs Ka, Kb, and Kc determine the modulus ("divided by" number) for the first and last count segments according to the truth table shown in Table 1. Each time the first (fastest) count segment goes through a cycle, it decrements the number that is preset (disturbed) in the middle count segment by 1, and the last count segment by 30. The last count segment consists of flip-flops that are not required to operate the first count segment. For example, in the *2 mode, only one flip-flop is required in the first count segment. Therefore, the last count segment has three flip-flops that can be preset to a maximum count of 7 with a bit value in the thousands. If the first segment requires -5-10, then Ka is set to 1, Kb is set to 1, and Kc is set to 0. Disturbance inputs J1, J2, J3 and J4 are used to preset the first count section, there is no "last count section". The intermediate count section consists of three cascaded BCD decimal (-5-10) counters and can be preset via disturbance inputs J5 to J16.