Overview

Product details

This synchronous 4-bit binary counter features an internal carry look-ahead feature. Synchronous operation is achieved by clocking all flip-flops simultaneously, a mode of operation that eliminates output count spikes commonly associated with asynchronous (ripple clock) counters. The buffered clock input triggers the four flip-flops on the rising (positive going) edge of the clock input waveform. The counter is fully programmable, setting a low level at the load input disables the counter and causes the output to coincide with the set data after the next clock pulse, regardless of the level of the enable input. If the enable input is high at or before the transition, a low to high transition at the load input can be avoided when the clock is low. The clear function is asynchronous, a low level at the clear input sets all four flip-flop outputs low after the next clock pulse, regardless of the level of the enable input. This synchronous clear allows the count length to be easily modified, as the maximum count required for decoding can be accomplished with a single external NAND gate. The gate output is connected to the clear input to clear synchronously with LLLL.